DK-DEV-5SGXEA7N【PDF 264/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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9-4

CRC Calculation Time

SV51011

2014.01.10

Table 9-2: Error Detection Frequency Range for Stratix V Devices

The following table lists the frequencies and valid values of n.

Internal Oscillator Frequency

Error Detection Frequency

Maximum Minimum

n

Divisor Range

100 MHz

100 MHz

390 kHz

0, 1, 2, 3, 4, 5, 6, 7, 8 1 – 256

CRC Calculation Time

The time taken by the error detection circuitry to calculate the CRC for each frame is determined by the

device in use and the frequency of the error detection clock.

You can calculate the minimum and maximum time for any number of divisor based on the following

formula:

Maximum time ( n ) = 2^( n -8) * maximum time

Minimum time ( n ) = 2^ n * minimum time

where the range of n is from 0 to 8.

Table 9-3: CRC Calculation Time in Stratix V Devices

The following table lists the minimum and maximum time taken to calculate the CRC value:

? The minimum time is derived using the maximum clock frequency with a divisor of 0.

? The maximum time is derived using the minimum clock frequency with a divisor of 8.

Variant

Member Code

A3

Package

EH29-H780

HF35-F1152

KF35-F1152

Minimum Time (ms)

38

38

38

Maximum Time (s)

19.42

19.42

19.42

A4

KF40-F1517/KH40-H1517

38

38

19.42

19.42

Stratix V GX

A5

A7

47

47

24.20

24.20

A9

AB

B5

B6

All

68

68

45

45

35.21

35.21

23.52

23.52

Stratix V GT

C5

C7

All

47

47

24.20

24.20

Altera Corporation

SEU Mitigation for Stratix V Devices

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